This invention relates to microelectronic devices and fabrication methods, and more particularly to gallium nitride semiconductor devices and fabrication methods therefor.
Gallium nitride is being widely investigated for microelectronic devices including but not limited to transistors, field emitters and optoelectronic devices. It will be understood that, as used herein, gallium nitride also includes alloys of gallium nitride such as aluminum gallium nitride, indium gallium nitride and aluminum indium gallium nitride.
A major problem in fabricating gallium nitride-based microelectronic devices is the fabrication of gallium nitride semiconductor layers having low defect densities. It is known that one contributor to defect density is the substrate on which the gallium nitride layer is grown. Accordingly, although gallium nitride layers have been grown on sapphire substrates, it is known to reduce defect density by growing gallium nitride layers on aluminum nitride buffer layers which are themselves formed on silicon carbide substrates. Notwithstanding these advances, continued reduction in defect density is desirable.
It also is known to produce low defect density gallium nitride layers by forming a mask on a layer of gallium nitride, the mask including at least one opening therein that exposes the underlying layer of gallium nitride, and laterally growing the underlying layer of gallium nitride through the at least one opening and onto the mask. This technique often is referred to as xe2x80x9cEpitaxial Lateral Overgrowthxe2x80x9d (ELO). The layer of gallium nitride may be laterally grown until the gallium nitride coalesces on the mask to form a single layer on the mask. In order to form a continuous layer of gallium nitride with relatively low defect density, a second mask may be formed on the laterally overgrown gallium nitride layer, that includes at least one opening that is offset from the opening in the underlying mask. ELO then again is performed through the openings in the second mask to thereby overgrow a second low defect density continuous gallium nitride layer. Microelectronic devices then may be formed in this second overgrown layer. ELO of gallium nitride is described, for example, in the publications entitled Lateral Epitaxy of Low Defect Density GaN Layers Via Organometallic Vapor Phase Epitaxy to Nam et al., Appl. Phys. Lett. Vol. 71, No. 18, Nov. 3, 1997, pp. 2638-2640; and Dislocation Density Reduction Via Lateral Epitaxy in Selectively Grown GaN Structures to Zheleva et al, Appl. Phys. Lett., Vol. 71, No. 17, Oct. 27, 1997, pp. 2472-2474, the disclosures of which are hereby incorporated herein by reference.
It also is known to produce a layer of gallium nitride with low defect density by forming at least one trench or post in an underlying layer of gallium nitride to define at least one sidewall therein. A layer of gallium nitride is then laterally grown from the at least one sidewall. Lateral growth preferably takes place until the laterally grown layers coalesce within the trenches. Lateral growth also preferably continues until the gallium nitride layer that is grown from the sidewalls laterally overgrows onto the tops of the posts. In order to facilitate lateral growth and produce nucleation of gallium nitride and growth in the vertical direction, the top of the posts and/or the trench floors may be masked. Lateral growth from the sidewalls of trenches and/or posts also is referred to as xe2x80x9cpendeoepitaxyxe2x80x9d and is described, for example, in publications entitled Pendeo-Epitaxy: A New Approach for Lateral Growth of Gallium Nitride Films by Zheleva et al., Journal of Electronic Materials, Vol. 28, No. Feb. 4, 1999, pp. L5-L8; and Pendeoepitaxy of Gallium Nitride Thin Films by Linthicum et al., Applied Physics Letters, Vol. 75, No. Jul. 2, 1999, pp. 196-198, the disclosures of which are hereby incorporated herein by reference.
ELO and pendeoepitaxy can provide relatively large, low defect gallium nitride layers for microelectronic applications. However, a major concern that may limit the mass production of gallium nitride devices is the growth of the gallium nitride layers on a silicon carbide substrate. Notwithstanding silicon carbide""s increasing commercial importance, silicon carbide substrates still may be relatively expensive. Moreover, it may be difficult to use silicon carbide substrates in optical devices, where back illumination may be desired, because silicon carbide is opaque Accordingly, the use of an underlying silicon carbide substrate for fabricating gallium nitride microelectronic structures may adversely impact the cost and/or applications of gallium nitride devices.
The present invention pendeoepitaxially grows sidewalls of posts in an underlying gallium nitride layer that itself is on a sapphire substrate, by treating the underlying gallium nitride layer and/or the sapphire substrate to prevent vertical growth of gallium nitride from the trench floor from interfering with the pendeoepitaxial growth of the gallium nitride sidewalls of the posts. Thus, widely available sapphire substrates may be used for pendeoepitaxial of gallium nitride, to thereby allow reduced cost and/or wider applications for gallium nitride devices.
More specifically, gallium nitride semiconductor layers may be fabricated by etching an underlying gallium nitride layer on a sapphire substrate, to define at least one post in the underlying gallium nitride layer and at least one trench in the underlying gallium nitride layer. The at least one post includes a gallium nitride top and a gallium nitride sidewall. The at least one trench includes a trench floor. The gallium nitride sidewalls are laterally grown into the at least one trench, to thereby form a gallium nitride semiconductor layer. However, prior to performing the laterally growing step, the sapphire substrate and/or the underlying gallium nitride layer is treated to prevent growth of gallium nitride from the trench floor from interfering with the lateral growth of the gallium nitride sidewalls of the at least one post into the at least one trench.
The sapphire substrate may be etched beneath the at least one trench sufficiently deep to create a sapphire floor and to prevent vertical growth of gallium nitride from the sapphire floor from interfering with the lateral growth of the gallium nitride sidewalls of the at least one post into the at least one trench. Alternatively or in addition, the trench floor may be masked with a mask. In yet other alternatives, the underlying gallium nitride layer is selectively etched to expose the sapphire substrate and create a sapphire floor. The gallium nitride post tops also may be masked to reduce nucleation of gallium nitride thereon, compared to on gallium nitride. Following growth, at least one microelectronic device may be formed in the gallium nitride semiconductor layer.
Even more specifically, an underlying gallium nitride layer on a sapphire substrate is etched to selectively expose the sapphire substrate and define at least one post and at least one trench in the underlying gallium nitride layer. The at least one post each includes a gallium nitride top and a gallium nitride sidewall. The at least one trench includes a sapphire floor. The gallium nitride sidewall of the at least one post is grown laterally into the at least one trench, to thereby form a gallium nitride semiconductor layer.
Preferably, when etching the underlying gallium nitride layer on the sapphire substrate, the sapphire substrate is etched as well, to define at least one post in the underlying gallium nitride layer and in the sapphire substrate, and at least one trench in the underlying gallium nitride layer and in the sapphire substrate. The at least one post each includes a gallium nitride top, a gallium nitride sidewall and a sapphire sidewall. The at least one trench includes a sapphire floor. More preferably, the sapphire substrate is etched sufficiently deep to prevent vertical growth of gallium nitride from the sapphire floor from interfering with the step of laterally growing the gallium nitride sidewalls of the at least one post into the at least one trench. For example, the sapphire sidewall height to sapphire floor width ratio exceeds about 1/4. In another embodiment, the sapphire floor is masked with a mask that reduces nucleation of gallium nitride thereon compared to on sapphire.
In yet other embodiments, the sapphire substrate includes an aluminum nitride buffer layer thereon. During the etching step, the gallium nitride layer and the aluminum nitride buffer layer both are etched to selectively expose the sapphire substrate. In other embodiments, the sapphire substrate also is selectively etched so that the trenches extend into the sapphire substrate.
Lateral growth preferably proceeds pendeoepitaxially by laterally overgrowing the gallium nitride sidewall onto the gallium nitride top, to thereby form a gallium nitride semiconductor layer. Prior to pendeoepitaxial growth, the gallium nitride top may be masked with a mask that reduces nucleation of gallium nitride thereon compared to on gallium nitride.
According to another aspect of the present invention, the trench floor may be masked with a mask, thereby obviating the need to expose the sapphire substrate. Specifically, an underlying gallium nitride layer on a sapphire substrate may be etched to define at least one post in the underlying gallium nitride and at least one trench in the underlying gallium nitride layer. The at least one post includes a top and a sidewall and the at least one trench includes a trench floor. The at least one floor is masked with a mask, and the sidewall of the at least one post is laterally grown into the at least one trench, to thereby form a gallium nitride semiconductor layer. As was described above, the post tops also may be masked. Preferably, the at least one floor and the at least one top are masked simultaneously, for example by performing a directional deposition that forms a mask on the lateral tops and floors, but not on the sidewalls. As also was described above, when an aluminum nitride buffer layer is present, it may be etched to define the posts and trenches, or the mask may be formed on the aluminum nitride buffer layer. In another alternative, the trench floor may be located in the gallium nitride layer itself, and the gallium nitride trench floor may be masked as was described above.
Embodiments of gallium nitride semiconductor structures according to the present invention can include a sapphire substrate and an underlying gallium nitride layer on the sapphire substrate. The underlying gallium nitride layer includes therein at least one post and at least one trench. The at least one post each includes a gallium nitride top and a gallium nitride sidewall. The at least one trench includes a sapphire floor. A lateral gallium nitride layer extends laterally from the gallium nitride sidewall of the at least one post into the at least one trench. In a preferred embodiment, the at least one trench extends into the sapphire substrate such that the at least one post each includes a gallium nitride top, a gallium nitride sidewall and a sapphire sidewall and the at least one trench includes a sapphire floor. The sapphire floor preferably is free of a vertical gallium nitride layer thereon and the sapphire sidewall height to sapphire floor width ratio may exceed about 1/4. A mask may be included on the sapphire floor and an aluminum nitride buffer layer also may be included between the sapphire substrate and the underlying gallium nitride layer. A mask also may be included on the gallium nitride top. The mask on the floor and the mask on the top preferably comprise same material.
Other embodiments of gallium nitride semiconductor structures according to the present invention also can include a sapphire substrate and an underlying gallium nitride layer on the sapphire substrate. The underlying gallium nitride layer includes therein at least one post and at least one trench. The at least one post includes a gallium nitride top and a gallium nitride sidewall, and the at least one trench includes a trench floor. A mask is included on the at least one trench floor, and the gallium nitride layer extends laterally from the gallium nitride sidewall of the at least one post into the at least one trench. In a preferred embodiment, the trench floor is a sapphire floor. A mask may be provided on a gallium nitride top that preferably comprises the same material as the mask on the trench floor. An aluminum nitride buffer layer also may be provided, as was described above. At least one microelectronic device may be formed in the gallium nitride semiconductor layer.
Accordingly, sapphire may be employed as a substrate for growing gallium nitride semiconductor layers that can have low defect densities. Low cost and/or high availability gallium nitride devices thereby may be provided.